FPC and PIC

FPC 

-- M/T/MX-Series Flexible PIC Controller that slides into a chassis slot

   The "carrier card" (or controller card in Cisco-speak) that allows you to slot interface cards

reference:

https://www.juniper.net/techpubs//en_US/release-independent/junos/topics/concept/m20-overview-nog.html

http://forums.juniper.net/t5/Junos/PIM-PIC-FPC-explanation/td-p/26118

RAM series in ascending order based on the year of introuduction
1. RAM
2.DRAM
3.SDRAM
4.DDR1,DDR2,DDR3

Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming commands. The data storage area is divided into several banks, allowing the chip to work on several memory access commands at a time, interleaved among the separate banks. This allows higher data access rates than an asynchronous DRAM

Speed

The main difference between SDRAM and DDR memory is the doubled speed: DDR can transfer data at roughly twice the speed of SDRAM. PC133 SDRAM runs at 133 MHz, while 133 MHz DDR effectively runs at 133 MHz x 2 = 266 Mhz.

reference:

http://www.diffen.com/difference/DDR_vs_SDRAM

http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory